company blog about ADI AD9211BCPZ-250 10-Bit 250 MSPS 1.8V Monolithic Sampling Analog-to-Digital Converter

ADI AD9211BCPZ-250 10-Bit 250 MSPS 1.8V Monolithic Sampling Analog-to-Digital Converter

AD9211BCPZ-250 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9211BCPZ-250 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).

Specifications of AD9211BCPZ-250

Resolution：10 bit

Number of Channels：1 Channel

Interface Type：SPI

Sampling Rate：250 MS/s

Input Type：Differential

Architecture：Pipeline

Analogue Supply Voltage：1.7 V to 1.9 V

Digital Supply Voltage：1.7 V to 1.9 V

SNR - Signal to Noise Ratio：59.4 dB

Minimum Operating Temperature：- 40 C

Maximum Operating Temperature：+ 85 C

DNL - Differential Nonlinearity：+/- 0.5 LSB

Gain Error：4.3 %FSR

Height：0.83 mm

INL - Integral Nonlinearity：+/- 0.45 LSB

Input Voltage：1.25 Vp-p

Length：8 mm

Moisture Sensitive：Yes

Number of ADC Inputs：1 Input

Number of Converters：1 Converter

Operating Supply Voltage：1.8 V

Pd - Power Dissipation：437 mW

Power Consumption：380 mW

Supply Voltage - Max：1.8 V

Supply Voltage - Min：1.8 V

Width：8 mm

Unit Weight：170 mg

Features of AD9211BCPZ-250

SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS

ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)

SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)

Excellent linearity

DNL = ±0.1 LSB typical

INL = ±0.2 LSB typical

LVDS at 300 MSPS (ANSI-644 levels)

700 MHz full power analog bandwidth

On-chip reference, no external decoupling required

Integrated input buffer and track-and-hold

Low power dissipation

437 mW @ 300 MSPS—LVDS SDR mode

410 mW @ 300 MSPS—LVDS DDR mode

Programmable input voltage range

1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation

Selectable output data format (offset binary, twos complement, Gray code)

Highlight of AD9211BCPZ-250

High Performance—Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input.

Low Power—Consumes only 410 mW @ 300 MSPS.

Ease of Use—LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation.

Pin-Compatible Family—12-bit pin-compatible family offered as AD9230.

Applications of AD9211BCPZ-250

Wireless and wired broadband communications

Cable reverse path

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization

Functional Block Diagram of AD9211BCPZ-250