company blog about ST Microprocessor-MPU STM32MP257FAL3 32-Bit Dual ARM Cortex-A35,ARM Cortex-M33 Microprocessor IC

ST Microprocessor-MPU STM32MP257FAL3 32-Bit Dual ARM Cortex-A35,ARM Cortex-M33 Microprocessor IC

Product Description
STM32MP257FAL3 devices provide an external SDRAM interface supporting external memories up to 32‑Gbit density (4 Gbytes), 16- or 32-bit DDR3L up to 1066 MHz, 16- or 32-bit LPDDR4 or DDR4 up to 1200 MHz. The SDRAM content can be encrypted with AES-128.

Feature
LCD-TFT controller, up to 24-bit // RGB888
Up to FHD (1920 × 1080) @60 fps
3 layers including a secure layer
YUV support, 90° output rotation
Optional MIPI DSI®, 4× data lanes, up to 2.5 Gbit/s each
Up to QXGA (2048 × 1536) @60 fps
Optional FPD-1 and OpenLDI JEIDA/VESA (LVDS), up to 2× links of 4× data lanes, up to 1.1 Gbit/s per lane
Up to QXGA (2048 × 1536) @60 fps
Optional NPU: VeriSilicon® - Up to 900 MHz
TensorFlowLite - ONNX - Linux NN
Video processing
Optional hardware video encoder and decoder up to 600 MHz
H264/VP8 up to FHD (1920×1080) @60 fps
JPEG up to 500 Mpixel/s
128 Kbytes of video RAM
4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
3× 16-bit advanced motor control timers
10× 16-bit general-purpose timers (including 2 basic timers without PWM)
5× 16-bit low-power timers
Secure RTC with subsecond accuracy and hardware calendar
Up to 2× 4 Cortex®-A35 system timers (secure, non-secure, virtual, hypervisor)
2× SysTick Cortex®-M33 timer (secure, non-secure)
1× SysTick Cortex®-M0+ timer
7× watchdogs (5× independent and 2× window)