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Supply Lattice LAE5UM-25F-6BG381E Field Programmable Gate Array IC
Product Description
LAE5UM-25F-6BG381E is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SerDes and high speed source synchronous interfaces in an economical FPGA fabric.
Feature
Higher Logic Density for Increased System Integration
12K to 44K LUTs
197 to 203 user-programmable I/O
Embedded SerDes
270 Mb/s, up to 3.2 Gb/s, SerDes interface (ECP5UM Automotive)
Supports eDP in RDR (1.62 Gb/s) and HDR (2.7 Gb/s)
Up to four channels per device: PCI Express,Ethernet (1GbE, XAUI, and SGMII,), and CPRI
Fully cascadable slice architecture
12 to 160 slices for high performance multiply and accumulate
Powerful 54-bit ALU operations
Time Division Multiplexing MAC Sharing
Rounding and truncation
Each slice supports
Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers
Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate
(MMAC) operations
Flexible Memory Resources
Up to 1.944 Mb sysMEM™ Embedded Block RAM (EBR)
194k to 351k bits distributed RAM
sysCLOCK Analog PLLs and DLLs
Four DLLs and four PLLs in LAE5-45; two DLLs and two PLLs in LAE5-25 and LAE5-12
Pre-engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated read/write levelling functionality
Dedicated gearing logic
Source synchronous standards support
ADC/DAC, 7:1 LVDS, XGMII
High Speed ADC/DAC devices