company blog about 【TI DSP Product】TMS320DM642AGDK7:Video/Imaging Fixed-Point Digital Signal Processor

【TI DSP Product】TMS320DM642AGDK7:Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642AGDK7 is high-performance Video/Imaging Fixed-Point Digital Signal Processor.

The TMS320DM642AGDK7 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The TMS320DM642AGDK7 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

Product Attributes of TMS320DM642AGDK7
Type：Fixed Point
Interface：Host Interface, I2C, McASP, McBSP, PCI
Clock Rate：720MHz
Non-Volatile Memory：External
On-Chip RAM：160kB
Voltage - I/O：3.30V
Voltage - Core：1.40V
Operating Temperature：0°C ~ 90°C (TC)
Number of Cores: 1 Core
Program Memory Size: 16 kB
Data RAM Size: 256 kB
L1 Cache Instruction Memory: 16 kB
L1 Cache Data Memory: 16 kB
Data Bus Width: 32 bit
Moisture Sensitive: Yes
Number of I/Os: 16 I/O
Number of Timers/Counters: 3 x 32 bit
Unit Weight: 2.446 g

Feature of TMS320DM642AGDK7

• High-Performance Digital Media Processor

2-, 1.67-, 1.39-ns Instruction Cycle Time
500-, 600-, 720-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
4000, 4800, 5760 MIPS
Fully Software-Compatible With C64x™

• Instruction Set Features

Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2™ Increased Orthogonality

• L1/L2 Memory Architecture

128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)

• Endianess: Little Endian, Big Endian

• 64-Bit External Memory Interface (EMIF)

Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
1024M-Byte Total Addressable External Memory Space

• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)

• 10/100 Mb/s Ethernet MAC (EMAC)

IEEE 802.3 Compliant
Media Independent Interface (MII)
8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel

• Management Data Input/Output (MDIO)

• Three Configurable Video Ports

Providing a Glueless I/F to Common Video Decoder and Encoder Devices
Supports Multiple Resolutions and Video Standards

• VCXO Interpolated Control Port (VIC)

Supports Audio/Video Synchronization

• Host-Port Interface (HPI) [32-/16-Bit]

• 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2

• Multichannel Audio Serial Port (McASP)

Eight Serial Data Pins
Wide Variety of I2S and Similar Bit Stream Format
Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats

• Inter-Integrated Circuit (I2C) Bus™

• Two Multichannel Buffered Serial Ports

• Three 32-Bit General-Purpose Timers

• Sixteen General-Purpose I/O (GPIO) Pins

• Flexible PLL Clock Generator

• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

• 0.13-µm/6-Level Cu Metal Process (CMOS)

• 3.3-V I/O, 1.2-V Internal (-500)

• 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720)