AI Core FPGA XCVC1902-1MSEVSVD 1.9M Logic Cells 450MHz Field Programmable Gate Array

AI Core FPGA XCVC1902-1MSEVSVD 1.9M Logic Cells 450MHz Field Programmable Gate Array

Product Description Of XCVC1902-1MSEVSVD

XCVC1902-1MSEVSVD DC and AC characteristics are specified in extended (E) and industrial (I) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade and operating voltage (that is, the timing characteristics of a -1 speed grade extended (E) temperature range device operating at a VCCINT voltage of 0.80V (M) are the same as for a -1 speed grade industrial (I) temperature range device operating at a VCCINT voltage of 0.80V (M)).

Product Attributes Of XCVC1902-1MSEVSVD 

Features Of XCVC1902-1MSEVSVD

• The test conditions are configured for the generic Quad-SPI interface with a 12 mA drive strength, fast slew rate, and load conditions (15 pF/30 pF for a Quad-SPI device clock frequency up to 100 MHz and 15 pF for a Quad-SPI device clock frequency > 100 MHz), tested at 3.3V and 1.8V.
• 30 pF loads are for QSPI dual-stacked or QSPI dual-parallel modes.
• When the Quad-SPI device clock frequency is >37.5 MHz, the Quad-SPI loopback clock output (QSPI_LPBK_CLK) must be enabled in the control, interface, and processing system (CIPS), and the associated MIO[6] pin must be left unconnected on the board.
• The Quad-SPI reference clock frequency must be 2x the Quad-SPI device clock frequency when it is >37.5 MHz.
• TQSPICSCLK is only valid when two reference clock cycles are programmed between the chip select and clock.

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A: Yes,we support sample order and small order.Sample cost is different according to your order or project.
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Q: What about the lead time?
A: We can ship stock parts within 5 working days.If without stock,we will confirm lead time for you based on your order quantity.