Chip Integrated Circuit XCVC1902-2LSEVSVD Field Programmable Gate Array 1.9M Logic Cells

Chip Integrated Circuit XCVC1902-2LSEVSVD Field Programmable Gate Array 1.9M Logic Cells

Product Description Of XCVC1902-2LSEVSVD

XCVC1902-2LSEVSVD structure allows up to eight parallel memory access transactions every clock cycle, with five cycle access latency. Stall signals identify memory access conflicts during which time any outstanding memory operations are buffered. Each data memory module supports memory error detection (parity) and reporting.

Specification Of XCVC1902-2LSEVSVD

Features Of XCVC1902-2LSEVSVD

• Support peak LPDDR4 data rates in 486 I/O

• GTM transceivers can operate at data rates up to 112Gb/s by combining two transceivers together.

• The device can run 64 GTM transceivers at 112Gb/s.

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