M15T4G16256A–DEBG2G Memory IC Chip 933MHz DDR3 SDRAM Memory Chip BGA-96

M15T4G16256A–DEBG2G Memory IC Chip 933MHz DDR3 SDRAM Memory Chip BGA-96

Product Description Of M15T4G16256A–DEBG2G

M15T4G16256A–DEBG2G is 933MHz, 32M x 16 Bit x 8 Banks, DDR3(L) SDRAM Memory Chip, package is BGA-96.

DDR3(L) SDRAM uses a double data rate architecture to achieve high-speed operation.

The double datarate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3(L) SDRAM effectively consists of a single 8n-bit-wide, four clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Specification Of M15T4G16256A–DEBG2G

Features Of M15T4G16256A–DEBG2G

VDD = VDDQ =1.35V (1.283V ~ 1.45V)
Backward compatible to VDD = VDDQ = 1.5V ± 0.075V
– Supports DDR3L devices to bebackward compatible in 1.5V applications
Differential bidirectional data strobe
8n-bit prefetcharchitecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
Refresh cycle
- 64ms, 8192-cycle refresh at 0°C to +85°C
- 32ms, 8192-cycle refresh at +85°C to +95°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multi purpose register
Output driver calibration

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A:We can ship stock parts within 5 working days.If without stock,we will confirm lead time for you based on your order quantity.