SI5383A-D10188-GMR Integrated Circuit Chip 750MHz Network Synchronizer Clocks LGA56

SI5383A-D10188-GMR Integrated Circuit Chip 750MHz Network Synchronizer Clocks LGA56

Product Description Of SI5383A-D10188-GMR

SI5383A-D10188-GMR is Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs.
SI5383A-D10188-GMR combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra low jitter. The SI5383A-D10188-GMR is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization

Specification Of SI5383A-D10188-GMR

Features Of SI5383A-D10188-GMR

One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures
Input frequency range:
External crystal: 25-54 MHz
REF clock: 5-250 MHz
Diff clock: 8 kHz - 750 MHz
LVCMOS clock: 1 PPS, 8 kHz - 250MHz
Output frequency range:
Differential: 1 PPS, 100 Hz - 718.5 MHz
LVCMOS: 1 PPS, 100 Hz - 250 MHz
Ultra-low jitter of less than 150 fs

Applications Of SI5383A-D10188-GMR

Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2
Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1
Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.8273.2
IEEE 1588 (PTP) slave clock synchronization
Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization
1 Hz/1 PPS Clock Multiplier

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