88SE9215A1-NAA2C000 Integrated Circuit Chip One-Lane PCIe 2.0 To Four-Port 6Gbps SATA I/O Controller

88SE9215A1-NAA2C000 Integrated Circuit Chip One-Lane PCIe 2.0 To Four-Port 6Gbps SATA I/O Controller

Product Description Of 88SE9215A1-NAA2C000
88SE9215A1-NAA2C000 is a four-port, 3 Gbps or 6 Gbps SATA Host Bus Adapter that provides a one-lane PCIe 2.0 interface and SATA controller functions. The 88SE9215A1-NAA2C000 supplies four 6 Gbps SATA ports.

Features Of 88SE9215A1-NAA2C000
General
55 nm CMOS process, 1.0V digital core, 1.8V analog, and 3.3V I/O power supplies.
Reference clock frequency of 25 MHz, provided by an external clock source or generated byan external crystal oscillator.
PCIe
PCIe 2.0 endpoint device.
Compliant with PCIe 2.0 specifications.
Supports communication speed of 2.5 Gbps and 5 Gbps.
Supports AHCI programming interface registers for the SATA controller.
Supports aggressive power management.
Supports error reporting, recovery and correction.
Supports Message Signaled Interrupt (MSI).
SATA Controller
Compliant with Serial ATA Specification 3.1.
Supports communication speeds of 6 Gbps, 3 Gbps, and 1.5 Gbps.
Supports programmable transmitter signal levels.
Supports Gen 1i, Gen 1x, Gen 2i, Gen 2m, Gen 2x, and Gen 3i.
Supports four SATA ports.
Supports AHCI 1.0 programming interface.
Supports Native Command Queuing (NCQ).
Supports Port Multiplier FIS based switching or command based switching.
Supports Partial and Slumber Power Management states.
Supports Staggered Spin-up.
SPI Interface Controller
A four-pin interface provides read and write access to an external SPI flash or SPI ROMdevice.
Vendor specific information stored in the external device is read by the controller during thechip power-up.
PCI BootROMs of PCIe function 0 can also be stored in the external SPI device and readthrough the Expansion ROM BAR and the SPI interface controller.
Peripheral Interface Controller
Eight General Purpose I/O (GPIO) ports.
Each of the GPIO pins can be assigned to act as a general input or output pin.
Each of the GPIO inputs can be programmed to generate an edge-sensitive or alevel-sensitive maskable interrupt.
Each of the GPIO outputs can be programmed for a connected LED to blink at a user-definedfixed rate. The default rate is 100 ms.

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