W632GU6RB-11 Memory IC Chip 2Gbit DDR3L SDRAM 933MHz Low Voltage for Embedded Systems

The W632GU6RB-11 is a 2Gb DDR3L SDRAM memory chip. DDR3L is a low-voltage version of DDR3 that significantly reduces power consumption while maintaining high-speed data transfer capabilities, making it ideal for embedded systems with requirements for both power efficiency and bandwidth.

The W632GU6RB-11 features a 16M × 8 banks × 16-bit architecture, with a total capacity of 2Gb and a data bus width of 16 bits (x16). It supports a core voltage of 1.35 V (VDD) and an I/O voltage of 1.35 V/1.5 V (VDDQ), while remaining compatible with the standard 1.5 V I/O levels of DDR3, allowing for flexible selection during system design. The chip is housed in a 96-ball VFBGA package, measuring just 7.5 mm × 13 mm, making it suitable for space-constrained embedded applications.

• Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V
• Backward compatible to VDD, VDDQ = 1.5V ± 0.075V
• Double Data Rate architecture: two data transfers per clock cycle
• Eight internal banks for concurrent operation
• 8 bit prefetch architecture
• CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14
• Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-The-Fly (OTF)
• Programmable read burst ordering: interleaved or nibble sequential
• Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
• Edge-aligned with read data and center-aligned with write data
• DLL aligns DQ and DQS transitions with clock
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)
• Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency
• Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
• Auto-precharge operation for read and write bursts
• Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
• Precharged Power Down and Active Power Down
• Data masks (DM) for write data
• Programmable CAS Write Latency (CWL) per operating frequency
• Write Latency WL = AL + CWL
• Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
• System level timing calibration support via write leveling and MPR read pattern
• ZQ Calibration for output driver and ODT using external reference resistor to ground
• Asynchronous RESET# pin for Power-up initialization sequence and reset function
• Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
• Dynamic ODT mode for improved signal integrity and preselectable termination impedances during writes
• 2K Byte page size

• Embedded systems: Applications requiring medium-capacity high-speed caches, such as industrial control, human-machine interfaces (HMIs) and data acquisition terminals
• Network equipment: Data buffering in communication devices such as routers, switches and gateways
• Consumer electronics: Cost-sensitive consumer products such as digital televisions, set-top boxes and smart speakers
• Automotive electronics: In-vehicle infotainment systems and navigation devices (the industrial-grade temperature version must be selected)
• Industrial vision: Frame buffering for machine vision cameras and image capture cards