ADSP-TS201SABPZ050 Microcontroller MCU 500MHz TigerSHARC Processor With 24 Mbit On-Chip Embedded DRAM

ADSP-TS201SABPZ050 Microcontroller MCU 500MHz TigerSHARC Processor With 24 Mbit On-Chip Embedded DRAM

Product Description Of ADSP-TS201SABPZ050
ADSP-TS201SABPZ050 is one of the members of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, TigerSHARC Processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS201SABPZ050 features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC Processor to offer unrivaled DSP performance. At a 600 MHz clock rate, the ADSP-TS201SABPZ050 offers the industry's highest 16-bit fixed-point and 32-bit floating point performance. The ADSP-TS201SABPZ050 has a 1024-point complex FFT time of 16.8 microseconds and provides 1500 MFLOPs per watt.

Specifications Of ADSP-TS201SABPZ050

Feature Of ADSP-TS201SABPZ050
Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
High performance up to 600 MHz, 1.67 ns instruction rate DSP core
24 Mbit on-chip embedded DRAM internally organized in six banks with user-defined partitioning
Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC Processor to offer complete baseband processing
14 channel, zero overhead DMA controller
Four internal 128-bit wide internal buses providing a total memory bandwidth of 38.4 Gbytes per second
Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
Assembly and C language programmability
Temperature range -40°C to +85°C

Performance Of ADSP-TS201SABPZ050
High performance 600 MHz, 1.67 ns instruction rate DSP core
Executes eight 16-bit MACs with 40-bit accumulation or two 32-bit MACs with 80-bit accumulation per cycle
Executes six single-precision floating point or twenty four 16-bit fixed point operations per cycle (3.6 GFLOPS or 14.4 GOPS performance)
2-cycle, interlocked execution pipe
Parallelism allows the execution of up to four 32-bit instructions per cycle

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