MPC8569EVJAUNLB Microcontroller MCU PowerQUICC III Processor with 1.333 GHz 32-bit e500 Core in 783-pin FC-PBGA Package

MPC8569EVJAUNLB is designed to address the increasing performance requirements for broadband access equipment including 3G/WiMAX/LTE base stations, radio network controllers, gateways and ATM/TDM/IP equipment.

MPC8569EVJAUNLB helps facilitate both IP and multi-protocol solutions by combining a high-performance e500 processor core, built on Power Architecture® technology and scaling up to 1.33 GHz, with a flexible communications engine and high-speed system interfaces.

• High-performance, 32-bit e500 core, scaling up to 1.33 GHz, that implements the Power Architecture® technology
  • 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1)
  • 36-bit physical addressing
  • Double-precision embedded floating point APU using 64-bit operands
  • Embedded vector and scalar single-precision floating-point APUs using 32- or 64-bit operands
  • Memory management unit (MMU)
• Integrated L1/L2 cache
  • L1 cache--32-Kbyte data and 32-Kbyte instruction
  • L2 cache--512-Kbyte (8-way set associative)
• High-speed interfaces (multiplexed) supporting:
  • Two 1× Serial RapidIO interfaces (with message unit) or one 4x interface
  • ×4/×2/×1 PCI Express interface
  • Two SGMII interfaces
• On-chip network switch fabric
• 133 MHz, 16-bit, 3.3 V I/O, enhanced local bus (eLBC) with memory controller
• Enhanced secured digital host controller (eSDHC) used for SD/MMC card interface
• Integrated four-channel DMA controller
• Dual I2C and dual universal asynchronous receiver/transmitter (DUART) support
• Programmable interrupt controller (PIC)
• IEEE Std 1149.1™ JTAG test access port
• 1.0-V and 1.1-V core voltages with 3.3-V, 2.5-V, 1.8-V, 1.5-V and 1.0-V I/O
• 783-pin FC-PBGA package, 29 mm × 29 mm